TABLE OF CONTENTS Our model for the DLX CPU consists of an entity declaration and a behavioral architecture body. However, before we can write these units we need to define the types used in the external interface.
Figure 15-12 shows a package declaration that defines the types for the CPU ports, based on the predefined bit and bit-vector types and on the numeric bit-vector types defined in the IEEE numeric_bit package. The package also defines some other types that are useful in the model. The type dlx_address represents logic vectors used for address values, and the type dlx_word represents logic vectors used for data values. Dlx_word_array represents an array of data words and is used in the declaration of multiple output register entities. The type dlx_bus_word is a standard-logic vector used for the CPU tristate data bus. The constant disabled_dlx_word is the value driven by the CPU or memory onto the data bus when it is inactive. This corresponds to an inactive tristate driver. The type dlx_mem_width represents values driven on the CPU width port. The three constants define legal values for this type. Finally, dlx_debug_control is an enumeration type listing values that we use to control the amount of tracing information to be reported by the model. The model reports on its progress during a simulation, to help us debug the model. The values of the type are used as follows:
none: the model does not report any information;
msg_every_100_instructions: the model reports after...
