TABLE OF CONTENTS In this, our third case study, we develop a series of models of the DLX CPU, originally described by Hennessy and Patterson [7]. We first develop a behavioral model and test it using a test bench consisting of a memory and some instrumentation. Next, we refine the model to the register-transfer level. We test this version in a test bench that compares its outputs with those of the behavioral version.
The DLX CPU was originally designed by Hennessy and Patterson [7] as a vehicle for teaching principles of computer architecture. It is a simple reduced instruction set computer (RISC), very similar to many of the first generation of commercially available RISC CPUs. The designers describe it as the distilled essence of these CPUs. We use it here as the subject of a case study, showing how we might develop high-level models of complex devices such as a CPU. We start by describing the view of the CPU as seen by the machine language programmer and by the hardware designer interfacing the CPU with the rest of a computer system.
The DLX, like most RISC CPUs, has a relatively large number of general-purpose registers, as well as some special-purpose registers. These are all shown in Figure 15-1. Registers r1 to r31 are general-purpose registers that may be used to hold integers or any other 32-bit value. Register r0 is special in that it always has the value 0. Any value written into this...
