TABLE OF CONTENTS In this final case study, we develop a suite of VHDL entities for building queuing networks. These are used to model systems at a very high level of abstraction and to gain system performance estimates before proceeding to more detailed design. Our implementation of the queuing network entities illustrates the use of abstract data types and file input/output.
In all of the examples we have considered so far in this book, our main concern has been the correctness of the design. We have written models in VHDL and simulated them to verify that they correctly implement the required behavior. In our first chapter, we also mentioned performance analysis as a motivation for simulation. The requirements specification for a system often dictates that it must perform some number of operations per second or perform a task within a given amount of time. In such cases, it is important to verify that our initial high-level design meets the performance requirements. We may need to evaluate a number of alternative designs to choose one that meets the requirements with minimum cost. We would like to be able to evaluate a proposed design's performance before investing significant effort in refining it to a more detailed level.
One technique for system modeling to evaluate performance is uninterpreted modeling using queuing networks. This technique is described in many texts on computer performance analysis, including [9]. It involves modeling a system as an interconnected collection of servers, which process tokens
