15.5 Testing the Register-Transfer-Level Model

We can test our register-transfer-level CPU model using the same test bench that we used to test the behavioral model, as described in Section15.3. We need to modify the configuration declaration for the test bench to bind the register-transfer-level implementation to the processor component in the test bench. The revised configuration declaration is shown in Figure 15-60. In this version, the component configuration for the processor uses the configuration dlx_rtl, described in the previous section. That configuration refers to the entity work.dlx and selects the architecture rtl. We can then run our simulator, specifying the configuration dlx_test_rtl as the unit to simulate, to test the register-transfer-level model in the same way as we tested the behavioral model. The sequence of memory operations should be the same. The only observable difference should be that the CPU takes longer to execute each instruction. This is because our register-transfer-level model accurately describes the cycle-by-cycle operation of the CPU.

<b class="bold">configuration</b> dlx_test_rtl of dlx_test <b class="bold">is</b>    <b class="bold">for</b> bench        <b class="bold">for</b> cg : clock_gen             <b class="bold">use entity</b> work.clock_gen(behavior)                 <b class="bold">generic map</b> ( Tclk => 20 ns );        <b class="bold">end for;</b>        <b class="bold">for</b> mem : memory  ...