In this appendix, we provide sample answers to the quiz-style exercises marked with the symbol " ". Readers are encouraged to test their answers to the other, more involved, exercises by running the models on a VHDL simulator.

Chapter 1

1. Entity declaration: defines the interface to a module, in terms of its ports, their data transfer direction and their types. Behavioral architecture body: defines the function of a module in terms of an algorithm. Structural architecture body: defines an implementation of a module in terms of an interconnected composition of sub-modules. Process statement: encapsulates an algorithm in a behavioral description, contains sequential actions to be performed. Signal assignment statement: specifies values to be applied to signals at some later time. Port map: specifies the interconnection between signals and component instance ports in a structural architecture.

2.     apply_transform : <b class="bold">process is</b>    <b class="bold">begin</b>        d_out <= transform(d_in) <b class="bold">after</b> 200 ps;        <b class="bold">--</b> <i class="emphasis">debug_test <= transform(d_in);</i>        wait on enable, d_in;    <b class="bold">end process</b> apply_transform;

3. Basic identifiers: last_item. Reserved words: buffer. Invalid: prev item, value-1 and element#5 include characters that may not occur within identifiers; _control starts with an underscore; 93_999 starts with a digit; entry_ ends with an underscore.

4.     16#1#    16#22#    16#100.0#    16#0.8#

5. 12

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   44

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