In this appendix we present the full set of syntax rules for VHDL using the EBNF notation introduced in Chapter 1. The form of EBNF used in this book differs from that of the VHDL Language Reference Manual (LRM) in order to make the syntax rules more intelligible to the VHDL user. The LRM includes a separate syntax rule for each minor syntactic category. In this book, we condense the grammar into a smaller number of rules, each of which defines a larger part of the grammar. We introduce the EBNF symbols "(", ")" and "..." as part of this simplification. Our aim is to avoid the large amount of searching required when using the LRM rules to resolve a question of grammar.

Those parts of the syntax rules that were introduced in VHDL-93 or VHDL-2001 are underlined in this appendix. A VHDL-87 model may not use these features. In addition, there are some entirely new rules introduced in VHDL-93 that have no predecessors in VHDL-87, and futher rules introduced in VHDL-2001 that have no predecessors in VHDL-93 or VHDL-87. We identify these rules individually where they occur in this appendix.

Index to Syntax Rules

access_type_definition 689

actual_part 694

aggregate 695

alias_declaration 688

architecture_body 685

array_type_definition 689

assertion_statement 692

association_list 694

attribute_declaration 688

attribute_name 695

attribute_specification 688

based_integer 695

based_literal 695

binding_indication 688

bit_string_literal 695

block_configuration 686

block_declarative_item 691

block_statement 690

case_statement 693

character_literal 695

choices 695

component_declaration 688

component_instantiation_statement 692

component_specification 688

concurrent_assertion_statement 691

concurrent_procedure_call_statement 691

concurrent_signal_assignment_statement 691