TABLE OF CONTENTS We now turn our attention to the next level of refinement of our DLX CPU model: a register-transfer-level description. At this level, the CPU is composed of registers, buses, multiplexers, an ALU and a sequential control section. Figure 15-34 shows the register-transfer-level organization of the CPU upon which we base our VHDL model. It includes a register file for the general-purpose registers, individual registers for temporary storage (Temp), the program counter (PC), the memory address register (MAR), the memory data register (MDR) and the instruction register (IR). These all correspond to variables defined in the behavioral architecture of the CPU. The register-transfer-level CPU also contains a number of additional registers. The A and B registers are used to store values read from the register file, and the C register stores a result to be written into the register file. The multiplexer at the MDR input allows the MDR to be loaded from the destination bus or the external data bus. The other multiplexer allows the memory address to be selected from the PC value or the MAR value. Finally, the two modules labeled X1 and X2 are extension modules, which extend the 16-bit or 26-bit immediate field of an instruction to 32 bits for processing by the ALU. This data path interprets DLX instructions in a sequence of steps, many of which involve ALU operations. These steps each take one complete clock cycle. At the start of the cycle, the source operands are placed on the...
