TABLE OF CONTENTS Now that we have covered the basic modeling facilities provided by VHDL, we work through our first case study, the design of a pipelined multiplier accumulator (MAC) for a stream of complex numbers. Many digital signal processing algorithms, such as digital demodulation, filtering and equalization, make use of MACs. We use this design exercise to bring together concepts and techniques introduced in previous chapters.
A complex MAC operates on two sequences of complex numbers, { x i} and { y i}. The MAC multiplies corresponding elements of the sequences and accumulates the sum of the products. The result is
where N is the length of the sequences. Each complex number is represented in Cartesian form, consisting of a real and an imaginary part. If we are given two complex numbers x and y, their product is a complex number p, calculated as follows:
p real = x real y real - x imag y imag
p imag = x real y imag + x imag y real
The sum of x and y is a complex number s calculated as follows:
S real = x real + y real
S imag = x imag + y imag
Our MAC calculates its result by taking successive pairs of complex numbers, one each from the two input sequences, forming their complex product and adding...
