In the preceding chapters we have introduced most of the facilities provided by VHDL and shown how they may be used to model a variety of hardware systems at various levels of detail. However, there remain a few VHDL facilities that we have not yet discussed. In this chapter, we tie off these loose ends.

21.1 Buffer and Linkage Ports

When we introduced ports in Chapter 5, we identified three modes, in, out and inout, that control how data is passed to and from a design entity. VHDL provides two further modes, buffer and linkage. These modes may only be specified for ports of entities, blocks and components, not for generic constants or subprogram parameters.

A buffer mode port behaves in a similar way to an inout mode port, in that the port can be both read and assigned in the entity or block. The source of a buffer port determines the driving value of the port in the normal way. However, when the port is read, the value read is the driving value. This behavior differs from inout ports in that the value read for an inout port may be different from the driving value if the actual signal associated with the port is resolved. The behavior of a buffer port allows us to model a design that has a buffered output connection and internally uses the value driving the buffer. In this case we do not explicitly represent...