1.

[ 15.1/15.2] Write the 32-bit binary encoding for the following DLX instructions. (Note: The destination operand is written before source operands in DLX assembly language, and displacements in control transfer instructions are relative.)

1. j +48

2. beqz r3, +16

3. sll r2, r2, r5

4. multf f3, f7, f8

2.

[ 15.2] What string would be produced by the disassemble procedure for the bit vector X"2223002A"?

3.

[ 15.4] Trace the procedure calls in the register-transfer-level controller sequencer when the CPU fetches and executes each of the following instructions (assuming debug has the value none):

1. jump and link

2. branch (not taken)

3. branch (taken)

4. add with register operands

5. add with an immediate operand

6. load byte

7. set unsigned with an immediate operand

4.

[ 15.3/15.5] Develop a behavioral model of a direct-mapped write-through cache memory for inclusion in the DLX CPU test bench. The cache should use the burst-transfer protocol implemented by the memory to fetch cache lines.

5.

[ 15.4] Complete the register-transfer-level controller by writing the missing procedures:

bus_data_read, bus_data_write,do_EX_set_signed, do_EX_arith_logic_immed, do_EX_link, do_EX_lhi,do_MEM_jump, do_MEM_jump_reg and do_MEM_store.

6.

[ 15.2] Extend the behavioral model of the DLX to include interrupt handling. The entity interface is extended with an additional active-low input port, intreq_n, which is used by external input/output controllers to request interrupts. The CPU internal state is extended with a program status register (PSR) and an interrupt address register (IAR), accessed as special registers 0 and 1, respectively, using movi2s and movs2i instructions. The PSR...