TABLE OF CONTENTS Now that we have developed our behavioral CPU model, we can test it by writing a test-bench model. Since the function performed by the CPU is to execute a machine language program stored in memory, we can test the CPU by including a memory in the test bench. We preload the memory with a small program and monitor the ports of the CPU to verify that it is fetching and executing the program correctly. We also need to include a clock generator in the test bench to drive the clock and reset ports of the CPU.
Figure 15-28 shows the entity declaration and behavioral architecture body for the clock generator. The entity has a generic constant, Tclk, that is used to specify the clock period. The architecture body contains two processes, one to generate the reset signal and the other to generate the clock signal. The process reset_driver generates a single pulse on reset, starting at the beginning of a simulation and lasting three and a half clock periods. The process clock_driver initializes the clock signals to '0', then waits for a clock period. It then enters an infinite loop, in which it schedules the clock transitions for the next cycle and then waits for a cycle.
<b class="bold">entity</b> clock_gen <b class="bold">is</b> <b class="bold">generic</b> ( Tclk : delay_length ); <b class="bold">port </b>( clk : <b class="bold">out</b> bit; ...
