TABLE OF CONTENTS We now come to our second case study, in which we develop a package of procedures and functions to perform arithmetic operations on bit vectors. The subprograms treat the bit vectors as binary-encoded integers. This case study draws on the facilities of VHDL described in the previous three chapters.
VHDL provides certain predefined arithmetic operations, such as addition, subtraction, multiplication and division, on the predefined numeric types. However, while we may represent numbers with bit vectors by using a binary encoding, the language does not provide arithmetic operations for bit vectors. There are several alternative encoding schemes we may use to represent numbers, each with different interpretations of the bits within a vector. VHDL leaves the choice of representation to the designer. If we need to perform arithmetic operations on numbers represented as bit vectors, we must implement the operations according to the encoding we have chosen.
In this case study, we develop arithmetic operations for bit vectors that use conventional positional encoding to represent integers. We provide for both unsigned integers and signed integers using two's-complement representation. The bit-vector encodings for both number representations are shown in Figure 10-1. Each position in the bit vector has a corresponding weight, starting from 2 0 for the rightmost bit and increasing for positions further to the left. The difference between the two representations is that the weight of the leftmost bit is 2 n -1 for unsigned numbers but -2 n- 1 for signed...
