Since the main purpose of a model written in VHDL is to describe a hardware design, it should be made as easy as possible to read and understand. In this chapter, we introduce aliases as a means of making a model clearer. As in everyday use, an alias is simply an alternate name for something. We see how we can use aliases in VHDL for both data objects and other kinds of items that do not represent data in a model.

9.1 Aliases for Data Objects

If we have a model that includes a data object, such as a constant, a variable, a signal or, as we see in a later chapter, a file, we can declare an alias for the object with an alias declaration. A simplified syntax rule for this is

alias_declaration <span class="unicode">?</span> <b class="bold">alias</b> identifier <b class="bold">is</b> name ;

An alias declaration in this form simply defines an alternate identifier to refer to the named data object. We can refer to the object using the new identifier, treating it as being of the type specified in the original object's declaration. Operations we perform using the alias are actually applied to the original object. (The only exceptions are reading the 'simple_name, 'path_name and 'instance_name attributes and the attributes that provide information about the index ranges of an array. In these cases, the attributes refer to the alias name rather than the original object's name.)