TABLE OF CONTENTS The predefined types, subtypes and functions of VHDL are defined in a package called standard, stored in the library std. Each design unit in a design is automatically preceded by the following context clause:
<b class="bold">library</b> std, work; <b class="bold">use</b> std.standard.<b class="bold">all</b>;
so the predefined items are directly visible in the design. The package standard is listed here. The comments indicate which operators are implicitly defined for each explicitly defined type. These operators are also automatically made visible in design units. The types universal_integer and universal_real are anonymous types. They cannot be referred to explicitly.
<b class="bold">package</b> standard <b class="bold">is</b> <b class="bold">type</b> boolean is (false, true); -- <i class="emphasis">implicitly declared for boolean operands:</i> <i class="emphasis">-- "and", "or", "nand", "nor", "xor", "xnor", "not" return boolean</i> <i class="emphasis">-- "=", "/=", "<", "<=", ">", ">=" return boolean</i> <b class="bold">type</b> bit <b class="bold">is</b> ('0','1'); -- <i class="emphasis">implicitly declared for bit operands:</i> <i class="emphasis">-- "and", "or", "nand", "nor", "xor", "xnor", "not" return bit</i> <i class="emphasis">-- "=", "/=", "<", "<=", ">", ">=" return boolean</i> <b class="bold">type</b> character <b class="bold">is</b> ( nul, soh, stx, etx, eot, enq,...
