TABLE OF CONTENTS In this chapter we discuss some miscellaneous topics, but very important to phase-locked loop designers. Charge pumps are the perfect match to sequential phase detectors, converting their differential outputs to a single-ended output. Aside from this useful function, we shall discuss how they offer tracking and phase noise advantages over other loop configurations.
The digital counter was originally designed for logic circuits, but was soon applied to frequency synthesizers. The phase noise performance of digital counters is discussed in Chapter 12, but in this chapter we discuss design techniques for reducing phase noise and improving the performance of digital counters. We also discuss an alternative to the conventional digital counter.
Our final topic is delay-locked loops. It is often used to describe the early-late gate synchronizer which we will discuss in Chapter 11. In this chapter, we discuss the delay-locked loop used by digital designers to align clock phases.
In Chapter 2, we discussed the sequential phase detector as a component of frequency synthesizers. The sequential phase detector is superior to mixer-type phase detectors in many applications. Multiplying phase detectors are preferred for data synchronization circuits, but dual detectors can also be used [1]. The sequential phase detector provides these advantages: 1) extended phase detector range, 2) improved frequency acquisition, 3) insensitive to input signal levels.
A sequential phase detector is shown in Figure 1. This is a relatively simple implementation, as several improvements can be made to its operation [3] [4]. Figure...
