TABLE OF CONTENTS In this chapter, we will evaluate the digital phase-locked loops for phase inputs similar to the analysis of analog phase-locked loops in Chapter 4. This analysis will be on linearized transfer functions, and applies to the complete digital loops of Chapter 9 as well as the analog/digital phase-locked loops of Chapter 8.
After the linear analysis, we will examine the nonlinear response of the complete digital phase-locked loops. This provides information about acquisition, probability of acquisition, and probability of cycle slip. The phase noise of digital phase-locked loops is also of concern, and we perform an analysis of the phase error variance.
Using the linearized transfer functions of H c( z) and H e( z) = 1 ? H c( z), the error response, ?( z) of the digital phase-locked loop to the inputs, ?( z) and 
, is
In Equation 10-1, recall the divisor of 
for N( z) compensates for the input signal's amplitude being included within H c( z) and H e( z). In subsequent analysis in this section, we assume noiseless operation, N( z) ? 0, for the different inputs.
Figure 10.1 tabulates the different phase step, frequency step, and frequency ramp inputs for a digital phase-locked loop. A phase step input has a forcing function of 
, where ?? is the step size.
