TABLE OF CONTENTS This chapter provides an overview of SystemVerilog. The topics presented in this chapter include:
The origins of SystemVerilog
Technical donations that went into SystemVerilog
Highlights of key SystemVerilog features
SystemVerilog extends Verilog
SystemVerilog is a standard set of extensions to the IEEE 1364-2005 Verilog Standard (commonly referred to as Verilog-2005 ). The SystemVerilog extensions to the Verilog HDL that are described in this book are targeted at design and writing synthesizable models. These extensions integrate many of the features of the SUPERLOG and C languages. SystemVerilog also contains many extensions for the verification of large designs, integrating features from the SUPERLOG, VERA C, C++, and VHDL languages, along with OVA and PSL assertions. These verification assertions are in a companion book, SystemVerilog for Verification [1.].
This integrated whole created by SystemVerilog greatly exceeds the sum of its individual components, creating a new type of engineering language, a Hardware Description and Verification Language or HDVL. Using a single, unified language enables engineers to model large, complex designs, and verify that these designs are functionally correct.
SystemVerilog started as an Accellera standard
The specification of the SystemVerilog enhancements to Verilog began with a standards group under the auspices of the Accellera Standards Organization, rather than directly by the IEEE. Accellera is a non-profit organization with the goal of supporting the development and use of Electronic Design Automation (EDA) languages. Accellera is the combined...
