TABLE OF CONTENTS Verilog only has limited places in which designers can declare variables and other design information. SystemVerilog extends Verilog s declaration spaces in several ways. These extensions make it much easier to model complex design data, and reduce the risk of hard-to-find coding errors. SystemVerilog also enhances how simulation time units are defined.
The topics discussed in this chapter include:
Packages definitions and importing definitions from packages
$unit compilation declaration space
Declarations in unnamed blocks
Enhanced time unit definitions
Before examining in detail the many new data types that SystemVerilog offers, it is important to know where designers can define important information that is used in a design. To illustrate these new declaration spaces, this chapter will use several SystemVerilog data types that are not discussed until the following chapters. In brief, some of the new types used in this chapter are:
logic a 1-bit 4-state variable, like the Verilog reg type; can be declared as any vector size (discussed in Chapter 3).
enum an enumerated net or variable with a labeled set of values; similar to the C enum type, but with additional syntax and semantics for modeling hardware (discussed in Chapter 4).
typedef a user-defined data type, constructed from built-in types or other user-defined types, similar to the C typedef (discussed in Chapter 4).
struct a collection of variables that can be referred to individually or collectively, similar to the C struct type (discussed in...
