SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling, Second Edition

A.7: Specify Section

A.7 Specify Section

A.7.1 Specify block declaration

specify_block ::= <b class="bold">specify</b> { specify_item } <b class="bold">endspecify</b>specify_item ::=          specparam_declaration         pulsestyle_declaration         showcancelled_declaration         path_declaration         system_timing_checkpulsestyle_declaration ::=<b class="bold">          pulsestyle_onevent</b> list_of_path_outputs <b class="bold">;</b>         <b class="bold">pulsestyle_ondetect</b> list_of_path_outputs <b class="bold">;</b>showcancelled_declaration ::=<b class="bold">          showcancelled</b> list_of_path_outputs <b class="bold">;</b>         <b class="bold">noshowcancelled</b> list_of_path_outputs <b class="bold">;</b>

A.7.2 Specify path declarations

path_declaration ::=           simple_path_declaration <b class="bold">;</b>          edge_sensitive_path_declaration <b class="bold">;</b>          state_dependent_path_declaration <b class="bold">;</b>simple_path_declaration ::=           parallel_path_description <b class="bold">=</b> path_delay_value          full_path_description <b class="bold">=</b> path_delay_valueparallel_path_description ::=<b class="bold">          (</b> specify_input_terminal_descriptor [ polarity_operator ] <b class="bold">=></b> specify_output_terminal_descriptor <b class="bold">)</b>full_path_description ::=<b class="bold">          (</b> list_of_path_inputs [ polarity_operator ] <b class="bold">*></b> list_of_path_outputs <b class="bold">)</b>list_of_path_inputs ::=          specify_input_terminal_descriptor { <b class="bold">,</b> specify_input_terminal_descriptor }list_of_path_outputs ::= ...

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