TABLE OF CONTENTS The Verilog language provides a general purpose procedural block, called always, that is used to model a variety of hardware types as well as verification routines. Because of the general purpose application of the always procedural block, the design intent is not readily apparent.
SystemVerilog extends Verilog by adding hardware type-specific procedural blocks that clearly indicate the designer s intent. By reducing the ambiguity of the general purpose always procedural block, simulation, synthesis, formal checkers, lint checkers, and other EDA software tools can perform their tasks with greater accuracy, and with greater consistency between different tools.
SystemVerilog also provides a number of enhancements to Verilog tasks and functions. Some of these enhancements make the Verilog HDL easier to use, and others substantially increase the power of using tasks and functions for modeling large, complex designs.
The topics covered in this chapter include:
Combinational logic procedural blocks
Latched logic procedural blocks
Sequential logic procedural blocks
Task and function enhancements
an always procedural block is an infinite loop
The Verilog always procedural block is an infinite loop that repeatedly executes the statements within the loop. In order for simulation time to advance, the loop must contain some type of time control or event control. This can be in the form of a fixed delay, represented with the # token, a delay until an expression evaluates as true, represented with the wait keyword, or a...
