TABLE OF CONTENTS SystemVerilog enables modeling at a higher level of abstraction through the use of 2-state types, enumerated types, and user-defined types. These are complemented by new specialized always procedural blocks, always_comb, always_ff and always_latch. These and other new modeling constructs have been discussed in the previous chapters of this book.
This chapter shows how to use these new levels of model abstractions to effectively model logic such as finite state machines, using a combination of enumerated types and the procedural constructs presented in the previous chapters. Using SystemVerilog, the coding of finite state machines can be simplified and made easier to read and maintain. At the same time, the consistency of how different software tools interpret the Verilog models can be increased.
The SystemVerilog features presented in this chapter include:
Using enumerated types for modeling Finite State Machines
Using enumerated types with FSM case statements
Using always_comb with FSM case statements
Modeling reset logic with enumerated types and 2-state types
Section 4.2 on page 79 introduced the enumerated type construct that SystemVerilog adds to the Verilog language. This section provides additional guidelines on using enumerated types for modeling hardware logic such as finite state machines.
enumerated types have restricted values
Enumerated types provide a means for defining a variable that has a restricted set of legal values. The values are represented with labels instead of digital logic values.
enumerated types allow abstract FSM...
