TABLE OF CONTENTS SystemVerilog makes a significant extension to the Verilog language by allowing users to define new net and variable types. User-defined types allow modeling complex designs at a more abstract level that is still accurate and synthesizable. Using SystemVerilog s user-defined types, more design functionality can be modeled in fewer lines of code, with the added advantage of making the code more self-documenting and easier to read.
The enhancements presented in this chapter include:
Using typedef to create user-defined types
Using enum to create enumerated types
Working with enumerated values
The Verilog language does not provide a mechanism for the user to extend the language net and variable types. While the existing Verilog types are useful for RTL and gate-level modeling, they do not provide C-like variable types that could be used at higher levels of abstraction. SystemVerilog adds a number of new types for modeling at the system and architectural level. In addition, SystemVerilog adds the ability for the user to define new net and variable types.
typedef defines a user-defined type
SystemVerilog user-defined types are created using the typedef keyword, as in C. User-defined types allow new type definitions to be created from existing types. Once a new type has been defined, variables of the new type can be declared. For example:
<b class="bold">typedef int unsigned</b> uint;...uint a, b; // two variables of type uint
using typedef locally
User-defined types can be defined locally, in...
