TABLE OF CONTENTS This chapter brings together the many concepts presented in previous chapters of this book, and shows how the SystemVerilog enhancements to Verilog can be used to model large designs much more efficiently than with the standard Verilog HDL. The example presented in this chapter shows how SystemVerilog can be used to model at a much higher level of data abstraction than Verilog, and yet be fully synthesizable.
The design used as an example for this chapter is based upon an example from Janick Bergeron s Verification Guild [1.]. The original example is a non-synthesizable behavioral model written in Verilog (using the Verilog-1995 standard). The example is a description of a quad Asynchronous Transfer Mode (ATM) user-to-network interface and forwarding node. For this book, this example has been modified in three significant ways. First, the code has been re-written in order to use many SystemVerilog constructs. Second, the non-synthesizable behavioral models have been rewritten using the SystemVerilog synthesizable subset. Third, the model has been made configurable, so that it can be easily scaled from a 4x4 quad switch to a 16x16 switch, or any other desired configuration.
The example in this chapter illustrates how the use of SystemVerilog structures, unions, and arrays significantly simplifies the representation of complex design data. The use of interfaces and interface methods further simplifies the communication of complex data between the blocks of a design.
The SystemVerilog coding style used in this example also shows how the design can be...
