TABLE OF CONTENTS This chapter defines Transaction Level Modeling (TLM) as an adjunct to behavioral modeling. The chapter explains how TLM can be used, and shows how SystemVerilog is suited to TLM.
Behavioral modeling can be used to provide a high level executable specification for development of both RTL code and the testbench. Transaction level modeling allows the system executable specification to be partitioned into executable specifications of the subsystems.
The executable specifications shown in this chapter are generally not considered synthesizable. However, there are some tools called high level or behavioral synthesis tools which are able to handle particular categories of behavioral or transaction level modeling.
The topics covered in this chapter include:
Definition of a transaction
Transaction level model of a bus
Multiple slaves
Arbitration between multiple masters
Semaphores
Interfacing transaction level with register transfer level models
Behavioral modeling (or behavior level modeling) is a style where the state machines of the control logic are not explicitly coded.
An implicit state machine is an always block which has more than one event control in it. For instance, the following code generates a 1 pulse after the reset falls:
<b class="bold">always begin</b><b class="bold"> do</b> @(<b class="bold">posedge</b> clock) <b class="bold">while</b> (reset); @(<b class="bold">posedge</b> clock) a = 1; @(<b class="bold">posedge</b> clock) a = 0;<b class="bold">end</b>
An RTL description would have an explicit state register, as follows:
<b class="bold">logic</b> [1:0] state;<b class="bold">always_ff</b> @(<b class="bold">posedge</b> clock)<b class="bold"> if</b> (reset) state...
