SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling, Second Edition

A.5: UDP Declaration and Instantiation

A.5 UDP Declaration and Instantiation

A.5.1 UDP declaration

udp_nonansi_declaration ::=           { attribute_instance } <b class="bold">primitive</b> udp_identifier <b class="bold">(</b> udp_port_list <b class="bold">) ;</b>udp_ansi_declaration ::=           { attribute_instance } <b class="bold">primitive</b> udp_identifier <b class="bold">(</b> udp_declaration_port_list <b class="bold">) ;</b>udp_declaration ::=            udp_nonansi_declaration udp_port_declaration { udp_port_declaration }                  udp_body<b class="bold">            endprimitive</b> [ <b class="bold">:</b> udp_identifier ]           udp_ansi_declaration                  udp_body<b class="bold">            endprimitive</b> [ <b class="bold">:</b> udp_identifier ]           <b class="bold">extern</b> udp_nonansi_declaration           <b class="bold">extern</b> udp_ansi_declaration           { attribute_instance } <b class="bold">primitive</b> udp_identifier <b class="bold">( .* ) ;</b>            { udp_port_declaration }            udp_body<b class="bold">      endprimitive</b> [ <b class="bold">:</b> udp_identifier ]

A.5.2 UDP ports

udp_port_list ::= output_port_identifier <b class="bold">,</b> input_port_identifier {...

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