SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling, Second Edition

A.1: Source Text

A.1 Source Text

A.1.1 Library source text

library_text ::= { library_descriptions }library_descriptions ::=          library_declaration         include_statement         config_declaration         <b class="bold">;</b>library_declaration ::=<b class="bold">          library</b> library_identifier file_path_spec { <b class="bold">,</b> file_path_spec }                [ <b class="bold">-incdir</b> file_path_spec { <b class="bold">,</b> file_path_spec } ] <b class="bold">;</b>include_statement ::= <b class="bold">include</b> file_path_spec <b class="bold">;</b>

A.1.2 Configuration source text

config_declaration ::=<b class="bold">          config</b> config_identifier <b class="bold">;</b>                 design_statement                 { config_rule_statement }<b class="bold">          endconfig</b> [ <b class="bold">:</b> config_identifier ]design_statement ::= <b class="bold">design</b> { [ library_identifier <b class="bold">.</b> ] cell_identifier } <b class="bold">;</b>config_rule_statement ::=          default_clause liblist_clause         inst_clause liblist_clause         inst_clause use_clause         cell_clause liblist_clause         cell_clause use_clause         <b class="bold">;</b>default_clause...

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