TABLE OF CONTENTS SystemVerilog adds several enhancements to Verilog for representing large amounts of data. The Verilog array construct is extended both in how data can be represented and for operations on arrays. Structure and union types have been added to Verilog as a means to represent collections of variables.
This section presents:
Structures
Unions
Operations on structures and unions
Unpacked arrays
Packed arrays
Operations on arrays
Array foreach loop
Special system functions for working with arrays
The $bits sizeof system function
Design data often has logical groups of signals, such as all the control signals for a bus protocol, or all the signals used within a state controller. The Verilog language does not have a convenient mechanism for collecting common signals into a group. Instead, designers must use ad-hoc grouping methods such as naming conventions where each signal in a group starts or ends with a common set of characters.
structures are defined using a C-like syntax
SystemVerilog adds C-like structures to Verilog. A structure is a convenient way of grouping several pieces of related information together. A structure is declared using the struct keyword. Structure members can be any variable type, including user-defined types, and any constant type. An example structure declaration is:
<b class="bold">struct</b> {<b class="bold"> int</b> a, b; // 32-bit variables<b class="bold"> opcode_t</b> opcode; ...
