TABLE OF CONTENTS SystemVerilog adds several new operators and procedural statements to the Verilog language that allow modeling more concise synthesizable RTL code. Additional enhancements convey the designer s intent, helping to ensure that all software tools interpret the procedural statements in the same way. This chapter covers the operators and procedural statements that are synthesizable, and offers guidelines on how to properly use these new constructs.
This SystemVerilog features presented in this chapter include:
New operators
Enhanced for loop
New do while bottom testing loop
New foreach loop
New jump statements
Enhanced block names
Statement labels
Unique and priority decisions
++ and -- operators
SystemVerilog adds the ++ increment operator and the -- decrement operator to the Verilog language. These operators are used in the same way as in C. For example:
<b class="bold">for</b> (i = 0; i <= 31; i++ ) <b class="bold">begin</b> ...<b class="bold">end</b>
As in C, the increment and decrement operators can be used to either pre-increment/pre-decrement a variable, or to post-increment/post-decrement a variable. Table 7-1 shows the four ways in which the increment and decrement operators can be used.
| Statement | Operation | Description |
|---|---|---|
| j = i++; | post-increment | j is assigned the value of i, and then i is incremented by 1 |
| j = ++i; | pre-increment | i is incremented by 1, and j is... |
