TABLE OF CONTENTS This appendix contains the formal definition of the SystemVerilog standard. The definition is taken directly from Annex A of the IEEE 1800-2005 SystemVerilog Language Reference Manual (SystemVerilog LRM) [1.].
The formal definition of SystemVerilog is described in Backus-Naur Form (BNF). The variant of BNF used in this appendix is as follows:
Bold text represents literal words themselves (these are called terminals). For example: module.
Non-bold text (possibly with underscores) represents syntactic categories (i.e. non terminals). For example: port_identifier.
Syntactic categories are defined using the form: syntactic_category ::= definition
A vertical bar ( ) separates alternatives.
Square brackets ( [ ] ) enclose optional items.
Braces ( { } ) enclose items which can be repeated zero or more times.
[1.]Appendix A reprinted with permission from Annex A of the IEEE Std. 1800-2005 SystemVerilog: Unified Hardware Design, Specification and Verification Language by IEEE. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.
