Overview

SystemVerilog extends Verilog s built-in variable types, and enhances how literal values can be specified. This chapter explains these enhancements and offers recommendations on proper usage. A number of small examples illustrate these enhancements in context. Subsequent chapters contain other examples that utilize SystemVerilog s enhanced variable types and literal values. The next chapter covers another important enhancement to variable types, user-defined types.

The enhancements presented in this chapter include:

• Enhanced literal values

• define text substitution enhancements

• Time values

• New variable types

• Signed and unsigned types

• Variable initialization

• Static and automatic variables

• Casting

• Constants

3.1 Enhanced Literal Value Assignments

filling a vector with a literal value

In the Verilog language, a vector can be easily filled with all zeros, all Xs (unknown), or all Zs (high-impedance).

<b class="bold">parameter</b> SIZE = 64;<b class="bold">reg</b> [SIZE-1:0] data;data = 0;   // fills all bits of data with zerodata = 'bz; // fills all bits of data with Zdata = 'bx; // fills all bits of data with X

Each of the assignments in the example above is scalable. If the SIZE parameter is redefined, perhaps to 128, the assignments will automatically expand to fill the new size of data. However, Verilog does not provide a convenient mechanism to fill a vector with all ones. To specify a literal value with all bits set to one, a fixed size must be specified. For example:

data=64'hFFFFFFFFFFFFFFFF;

This last example is not scalable. If...