TABLE OF CONTENTS Successful electronics manufacturing means being responsive to the packaging and the assembly demands of both the IC and end product. Paramount to this success is the interconnect substrates that support Level 1.0 single chip and multichip packaging and the all important Level 2.0 printed wiring board (PWB). Technologies for the manufacture of these interconnects include:
Thin film
Thick film/Cofired ceramic (Chapters 13/14)
Laminate/Organic (Chapter 15) and,
Build Up Technology (BUT) A combination of laminate and thin film.
These multilevel interconnect structures are characterized by high wiring densities that combine fine line high conductivity traces and small interlevel vias. While the technologies discussed here are basically mature processes, all continue to evolve in response to device and end product requirements.
The thin film process incorporates relevant IC wafer manufacturing technology and methodology as well as applicable practices and procedures. The processing makes available a viable high volume, cost effective manufacturing scenario fully supporting the interconnect packaging and assembly needs of Levels 1.0 and 2.0.
When performed in a proper manufacturing environment, such as a cleanroom similar to that shown in Figure 12-1, the thin film process readily addresses the high density interconnection requirements dictated by current and future high performance ICs.
Table 12-1 lists current leading edge and state-of-the-art dimensional capabilities covering fine lines, spaces, via diameters and pitch using the thin film process.
