TABLE OF CONTENTS Multichip Packaging (MCP) defines a packaging option in which multiple die and/or packaged devices (SOICs, CSPs) are incorporated into a single package. The MCP may be considered as an alternative to an Application Specific Integrated Circuit (ASIC). Compared to the ASIC it is a viable option offering lower cost and faster time to market. It presents many advantages providing for a significant increase in packaging efficiency by replacing multiple packages with a single package (Figure 5-1). There is also a major reduction in overall size and weight.
MCP by definition includes the following types of packaging technologies:
The Hybrid Circuit (HC) or Hybrid Integrated Circuit (HIC)
The Multichip Module (MCMs)
3-D Packaging, and
System in Package (SiP) or System on Package (SoP).
Common to each is an interconnect substrate that together with chip & wire, TAB, and flip chip interconnects combine to complete the attachment and interconnection of multiple components, both actives and passives. The substrate, which serves as a physical support structure, provides the electrical interconnections between the various components and therefore must be fully supportive of the IC and the overall mechanical, thermal, and electrical requirements. Table 5-1 demonstrates one of the many benefits to be realized with MCP, not necessarily at the component level, but rather at the system level. As indicated, using DIPs, 28 PWBs, 5"x5" are required at the systems level. Using SMT reduces the number of PWBs, 6"x9",...
