HDL Programming Fundamentals: VHDL and Verilog
Teaching students the essentials of HDL and the functionality of the digital components of a system, this book includes several comprehensive projects to show HDL in practical application.
TABLE OF CONTENTS HDL Programming Fundamentals: VHDL and Verilog
Chapter 2: Data-Flow Descriptions
OVERVIEW
In This Chapter
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Understand the concept of data-flow description in both VHDL and Verilog.
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Understand events and concurrent statements.
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Identify the basic statements and components of data-flow descriptions, such as logical operators, signal-assignment statements, the statement "assign," time delays, and vectors.
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Review and understand the fundamentals of some digital logic systems, such as half adder, 2x1 multiplexer, 2x2 combinational array multiplier, 2-bit comparator, D-latch, ripple-carry adder, and carry-lookahead adder.
2.1 HIGHLIGHTS OF DATA-FLOW DESCRIPTION
Data flow is one type (style) of hardware description. Other types include behavioral, structural (gate level), switch level, mixed type, and mixed language. Listed below are some facts about data-flow descriptions:
Facts
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Data-flow descriptions simulate the system by showing how the signal flows from system inputs to outputs. For example, the Boolean function of the output or the logical structure of the system shows such a signal flow.
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Signal-assignment statements are concurrent. At any simulation time, all signal-assignment statements that have an event are executed concurrently.
2.2 STRUCTURE OF THE DATA-FLOW DESCRIPTION
Listing 2.1 shows HDL code describing a system using data-flow description. The entity (module) name is system. There are two inputs ( I1 and I2) and two outputs ( O1 and O2). Statements 1 and 2 are used to assign a value to the outputs O1 and O2. The signal assignment operator <= is used in VHDL, or the predefined word assign in Verilog, to assign a value to the left-hand side of...
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