4.3 BINDING

Binding in HDL is common practice. Binding (linking) segment1 in HDL code to segment2 makes all information in segment2 visible to segment1. Consider the VHDL code in Listing 4.3.

entity one isport (I1, I2 : in std_logic; O1 : out std_logic);end one;architecture A of one issignal s : std_logic;..........end A;architecture B of one issignal x : std_logic;.......end B;

Architecture A is bound to entity one through the predefined word of. Also, architecture B is bound to entity one through the predefined word of. Accordingly, I1, I2, and O1 can be used in both architecture A and architecture B. Architecture A is not bound to architecture B, and hence signal s is not recognized in architecture B. Likewise, signal x is not recognized in architecture A.

Now consider Listing 4.4 where an entity is bound to a component.

entity orgate isport (I1, I2 : in std_logic; O1 : out std_logic);end orgate;architecture Or_dataflow of orgate isbeginO1 <= I1 or I2;end Or_dataflow;entity system isport (x, y, z : in std_logic; out r : std_logic_vector (3 downto 0);end system;architecture system_str of system iscomponent orgateport (I1, I2 : in std_logic; O1 : std_logic);end component;beginorgate port map (x, y, r(0));.......end system_str;

The component orgate is bound to the entity orgate because it has the same name. Architecture Or_dataflow