HDL Programming Fundamentals: VHDL and Verilog
Teaching students the essentials of HDL and the functionality of the digital components of a system, this book includes several comprehensive projects to show HDL in practical application.
TABLE OF CONTENTS HDL Programming Fundamentals: VHDL and Verilog
Chapter 6: Procedures, Tasks, and Functions
OVERVIEW
In This Chapter
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Understand the concept of procedures (VHDL), tasks (Verilog), and functions (both VHDL and Verilog).
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Review and understand how to convert between different types of data.
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Review signed vector multiplication.
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Understand a simple enzyme mechanism.
6.1 HIGHLIGHTS OF PROCEDURES, TASKS, AND FUNCTIONS
Facts
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Instead of writing the segment/construct every time it is used, a single call statement to a function, task, or a procedure that references this segment/construct is all that is needed.
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Procedures and tasks can have more than one input and more than one output. Functions have a single output, but can have more than one input.
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Procedures and functions in VHDL can be called only from within process. Tasks and functions in Verilog can be called only from within always or initial.
6.2 PROCEDURES AND TASKS
Procedures (VHDL) and tasks (Verilog) are similar to subroutines in other software languages, such as C. In many modules, a routine is repeatedly used, such as a multiplication algorithm, addition algorithm, or conversion between two numbering systems. Instead of writing these routines every time they are needed, the routines' codes can be stored as the body of a procedure (VHDL) or as the body of a task (Verilog). Whenever the routine needs to be executed, the procedure (task) is called by writing just one call statement. Section 6.2.1 discusses procedures, and Section 6.2.2 discusses tasks.
6.2.1 Procedures (VHDL)
Procedures are behavioral statements (see Chapter 3, "Behavioral Descriptions"). A procedure has two parts: the...
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