HDL Programming Fundamentals: VHDL and Verilog
Teaching students the essentials of HDL and the functionality of the digital components of a system, this book includes several comprehensive projects to show HDL in practical application.
TABLE OF CONTENTS HDL Programming Fundamentals: VHDL and Verilog
4.6: SUMMARY
4.6 SUMMARY
In this chapter, the fundamentals of structural description have been covered. Gate-level description has been discussed and used to build more-complex structures (macros). Verilog has built-in gates, such as and, or, nand, nor, and buf. Basic VHDL does not have built-in gates but we can build these gates by using the predefined word component. Both VHDL and Verilog have the predefined command generate for replicating structural macros. Table 4.11 shows a list of the VHDL statements covered in this chapter along with their Verilog counterparts (if any).
| VHDL | Verilog |
|---|---|
| generate | generate |
| port map | Built-in already. |
| and2, or2, xor2, nor2,xnor2, inv | and, or, xor, nor, xnor, not (The above gates are user-built.) |
| use library | Built-in already. |
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