HDL Programming Fundamentals: VHDL and Verilog
Teaching students the essentials of HDL and the functionality of the digital components of a system, this book includes several comprehensive projects to show HDL in practical application.
TABLE OF CONTENTS HDL Programming Fundamentals: VHDL and Verilog
4.2: ORGANIZATION OF THE STRUCTURAL DESCRIPTION
4.2 ORGANIZATION OF THE STRUCTURAL DESCRIPTION
Listing 4.1 shows a simple example of HDL code that describes a system, using structural description. The entity (VHDL) or module (Verilog) name is system; there are two inputs, a and b, and two outputs, sum and cout.
Listing 4.1: HDL Structural Description VHDL and Verilog
VHDL Structural Description
library IEEE;use IEEE.STD_LOGIC_1164.ALL; entity system is port (a, b : in std_logic;sum, cout : out std_logic); end system; architecture struct_exple of system is <i class="emphasis">--start declaring all different types of components</i> component xor2 port (I1, I2 : in std_logic; O1 : out std_logic); end component; component and2 port (I1, I2 : in std_logic; O1 : out std_logic); end component; begin <i class="emphasis">--Start of instantiation statements</i> X1 : xor2 port map (a, b, sum); A1 : and2 port map (a, b, cout); end struct_exple;
Verilog Structural Description
<span style="background-color:d9d9d9">module system (a, b, sum, cout);</span><span style="background-color:d9d9d9">input a, b;</span><span style="background-color:d9d9d9">output sum, cout;</span><span style="background-color:d9d9d9">xor X1 (sum, a, b);</span><span style="background-color:d9d9d9">/* X1 is an optional identifier; it can be omitted.*/</span><span style="background-color:d9d9d9">and a1 (cout,...
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