4.7 EXERCISES

4.1 Design a 4-bit parity generator. The output is 0 for even parity and 1 for odd parity. Write both the VHDL and Verilog codes.

4.2 Design a 3-bit priority encoder. The input I is 3-bit, and the output P is 3-bit. I(0), when high, has the highest priority, followed by I(1) and (I2). The output P for highest priority to lowest is 0, 1, and 2d, respectively. Construct a truth table, minimize, and write both the VHDL and Verilog codes.

4.3 In Listing 4.19, three 1-bit full adders were used for a 3-bit magnitude comparison. Modify the Listing by using one 3-bit adder macro.

4.4 Design a counter that counts 0, 2, 3, 5, 7, 0, 2, using the state machine approach. Show all details of your answer. Write both the VHDL and Verilog codes.

4.5 Referring to Listing 4.26 (Verilog), change the count from down to up and rewrite the code.

4.6 Translate the VHDL code shown in Listing 4.29 to Verilog. What is the logic function of the system?

library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity system is    Port (a, b, c : in std_logic; d, e : out std_logic );end system;architecture prob_6 of system iscomponent xor2port (I1, I2 : in std_logic; O1 : out std_logic);end component;component and2port (I1, I2 : in std_logic; O1 : out std_logic);end component;component or3port (I1, I2, I3 : in std_logic; O1 : out std_logic);end component;component invport (I1 : in std_logic; O1 : out...