HDL Programming Fundamentals: VHDL and Verilog

In This Chapter
Explore several advanced topics in HDL Description, such as file processing, character and string implementation, and the type record.
Understand VHDL Assert and Report statements.
Acquire a basic knowledge of artificial neural networks.
Files are valuable HDL description tools. For example, files can be used when dealing with a large amount of data that needs to be stored and accessed. Also, we may want to use files to display formatted output, such as reports. Files can be read or written. To read from or write to a file, it must be opened; and after reading or writing is finished, the file must be closed. A closed file cannot be accessed unless we open it. In Section 8.1.1, the VHDL file description is explored, and Section 8.1.2 discusses Verilog file descriptions.
File processing can be slightly different from one HDL simulator to another. Appropriate packages have to be attached to the VHDL module. The reader is advised to consult his VHDL package and simulator for files-handling capability. This section will present complete examples of file description with the names of the appropriate packages. Files have to be declared by the predefined object type file. File declaration includes the predefined word file followed by (in this order) the port direction or mode of the file (infile or outfile), a colon, and the subtype of the file. An example of file declaration is as follows:
file...