HDL Programming Fundamentals: VHDL and Verilog
Teaching students the essentials of HDL and the functionality of the digital components of a system, this book includes several comprehensive projects to show HDL in practical application.
TABLE OF CONTENTS HDL Programming Fundamentals: VHDL and Verilog
Appendix A: Creating a Project in Xilinx 7.1 Using VHDL or Verilog
In the following, we show the steps necessary to create a project using Xilinx ISE 1.7i Webpack. Although these steps are for ISE 1.7i, the same concepts here can be applied to other versions or to other vendors' products. These steps are for beginners. To find out more about this Webpack, go to: http://www.xilinx.com/ise/logic_design_prod/webpack.htm.
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Double-click on the Xilinx Project Navigator icon. From the toolbar, select File > New Project. A dialog box will open (see Figure A.1).
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In the New Project dialog box, type the desired location in the Project Location field, or browse to the directory under which you want to create your new project directory using the browse ( ) button next to the Project Location field.
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Enter the name of the project. In Figure A.1; the name entered is "fulladder."
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Click "Next" (see Figure A.2) and enter the appropriate information. In Figure A.2, the language is selected to be VHDL, and the simulator is ModelSim . The device is the chip where the HDL program, if desired, is downloaded after synthesis. If the desired language is Verilog, then select Verilog instead of VHDL.
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Click "Next" until you see the screen depicted in Figure A.3. This window summarizes the properties of the new project.
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Click "Finish" (see Figure A.4). The screen now shows the name of the project and the device.
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Attach the HDL module to your project. Click "Project" and select "New Source" (see Figure A.5).
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Since we are writing a VHDL module, select "VHDL...
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