HDL Programming Fundamentals: VHDL and Verilog
Teaching students the essentials of HDL and the functionality of the digital components of a system, this book includes several comprehensive projects to show HDL in practical application.
TABLE OF CONTENTS HDL Programming Fundamentals: VHDL and Verilog
Chapter 9: Mixed-Language Descriptions
OVERVIEW
In This Chapter
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Understand the concept of mixed-language description.
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Learn the advantages of mixing between VHDL and Verilog modules.
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Learn how to invoke a Verilog module from a VHDL module.
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Learn how to invoke a VHDL module from a Verilog module.
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Learn the current limitations of mixed-language descriptions.
9.1 HIGHLIGHTS OF MIXED-LANGUAGE DESCRIPTION
Facts
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To write HDL code in mixed-language, the simulator used with the HDL package should be able to handle a mixed-language environment.
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In the mixed-language environment, both VHDL and Verilog module files are made visible to the simulator.
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In the mixed-language environment, both VHDL and Verilog Libraries are made visible to the simulator.
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At the present time, the mixed-language environment has many limitations; but the development of simulators that can handle mixed-language environments with minimal constraints is underway. One of these major constraints is that a VHDL module can only invoke the entire Verilog module; and a Verilog module can only invoke a VHDL entity. For example, we cannot invoke a VHDL procedure from a Verilog module.
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Mixed-language description can combine the advantages of both VHDL and Verilog in one module. For example, VHDL has more-extensive file operations than Verilog, including write and read. By writing mixed-language, we can use the VHDL file operations in a Verilog module.
9.2 HOW TO INVOKE ONE LANGUAGE FROM THE OTHER
As mentioned, when writing VHDL code, you can invoke (import) a Verilog module; if you are writing Verilog code, you can invoke (import) a VHDL entity.
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