HDL Programming Fundamentals: VHDL and Verilog
Teaching students the essentials of HDL and the functionality of the digital components of a system, this book includes several comprehensive projects to show HDL in practical application.
TABLE OF CONTENTS HDL Programming Fundamentals: VHDL and Verilog
Appendix B: Summary of HDL Commands
The following list summarizes the major commands for both VHDL and Verilog.
I. GENERAL ORGANIZATION
| VHDL | Verilog |
|---|---|
|
library IEEE;use IEEE. STD_LOGIC_1164.ALL;entity indx isport(I1, I2 : in std_logic;I3 : bit_vector (5 downto 0); O1 : buffer bit);end;architecture anyname of indx issignal s1 : std_logic;begins1 <= I1;P1 : process (I1)variable s2 : std_logic;beginif (I1 = '0') thens2 := I1;elses2 := I2;end if;end process P1;end anyname; |
module indx(I1 , I2, I3, O1);output O1;input I1, I2;input [5:0] I3;wire s1;reg s2;assign s1 = I1;always @ (I1)beginif (I1 == 0)s2 = I1;elses2 = I2;endendmodule |
II. GATE-LEVEL DESCRIPTION
| VHDL | Verilog |
|---|---|
|
architecture gt_lvl of entity_name iscomponent andgate2port (I1, I2 : bit; O1 : out bit);end component;component orgate3port (I1, I2, I3 : bit; O1 : out bit);end component;for all : andgate2use entity work.name_entity (name_architecture);for all : andgate3use entity work.name_entity (name_architecture);begin--instantiation statementsa1 : andgate2port map (x, y, z);a2 : andgate3port map (x1, y1, y2, z);end gt_lvl; |
and (z, x, y);and(z, x1, y1 , y2, z); |
III. SWITCH-LEVEL DESCRIPTION
| VHDL | Verilog |
|---|---|
|
No built-inswitch level statements |
nmos n1 (drain, source, gate);pmos n1 (drain, source, gate);cmos (output, input, gn, gp);tran (dataio1, dataio2);trannif0 (dataio1, dataio2, control);tranif1 (dataio1, dataio2,control); |
IV. OPERATORS
| VHDL | Verilog |
|---|---|
| Arithmetic | |
| +, -, *, /, mod, **, (&) | +, -, *, /, %, **, {,} |
| Relational | |
| = , /=, <, <=; >, >= | ==, ! = , <, <=, >, >=, ===, !== |
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