4.5 GENERATE (HDL), GENERIC (VHDL), AND PARAMETER (VERILOC)

The predefined word generate is mainly used for repetition of concurrent statements. Its counterpart in behavioral description is the for-loop, and it can be used to replicate structural or gate-level description statements. Generate has several formats, one of which is covered here. See Chapter 7 for more formats.

In VHDL, the format for the generate statement is:

L1 : for i in 0 to N generatev1 : inv port map (Y(i), Yb(i));--other concurrent statementsend generate;

The above statement describes N + 1 inverters (assuming inv was declared as an inverter with input Y and output Yb); the input to inverter i is Y(i), and the output is Yb(i).L1 is a required label for the generate statement.

An equivalent generate statement in Verilog is:

generategenvar i;for (i = 0; i <= N; i = i + 1)    begin : uF    not (Yb[i], Y[i]);endendgenerate

The statement genvar i declares the index i of the generate statement; genvar is a predefined word. UF is a label for the predefined word begin; and begin must have a label.

In VHDL, generic, and parameter in Verilog, are used to define global constants. The generic statement can be placed within entity, component, or instantiation statements. The following generic VHDL statement inside the entity declares N as a global constant of value 3.

entity...