HDL Programming Fundamentals: VHDL and Verilog
Teaching students the essentials of HDL and the functionality of the digital components of a system, this book includes several comprehensive projects to show HDL in practical application.
TABLE OF CONTENTS HDL Programming Fundamentals: VHDL and Verilog
Chapter 10: Synthesis Basics
OVERVIEW
In This Chapter
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Understand the concept of synthesis.
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Learn how to map behavioral statements into logical gates and components.
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Learn how to verify your synthesis.
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Review and understand the fundamentals of digital-logic design for digital systems, such as adders, multiplexers, decoders, comparators, encoders, latches, flip-flops, counters, and memory cells.
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Understand the concept of sequential finite-state machines.
10.1 HIGHLIGHTS OF SYNTHESIS
This chapter will discuss the fundamentals of synthesis. Synthesis converts HDL behavioral code into logical gates or components. These logical gates and components can be downloaded into an electronic chip.
Facts
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Synthesis maps between the simulation (software) domain and the hardware domain.
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In this chapter, synthesis can be viewed as reverse engineering. The user is provided with the behavioral code and is asked to develop the logic diagram.
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Not all HDL statements can be mapped into the hardware domain. The hardware domain is limited to signals that can take zeros, ones, or that are left open. The hardware domain cannot differentiate, for example, between signals and variables, as does the simulation (software) domain.
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To successfully synthesize behavior code into a certain electronic chip, the mapping has to conform to the requirements and constrains imposed by the electronic chip vendor.
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Several synthesis packages are available on the market. These packages can take behavior code, map it, and produce a net list that is downloaded into the chip. In this chapter, we focus on learning how to synthesize the code manually, rather than on how to use the synthesizers.
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Two...
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