In the previous chapter we saw how to represent the internal state of models using VHDL-AMS data types and natures. In this chapter we look at how that data may be manipulated within processes and procedurals. This is done using sequential statements, so called because they are executed in sequence. We have already seen one of the basic sequential statements, the variable assignment statement, when we were looking at data types and objects. The statements we look at in this chapter deal with controlling actions within a model; hence they are often called control structures. They allow selection between alternative courses of action as well as repetition of actions.

3.1 If Statements

In many models, the behavior depends on a set of conditions that may or may not hold true during the course of simulation. We can use an if statement to express this behavior. The syntax rule for an if statement is

if_statement <span class="unicode">?</span>     [ <i class="emphasis">if</i>_label : ]     <b class="bold">if</b> <i class="emphasis">boolean_</i>expression <b class="bold">then</b>          { sequential_statement}     { <b class="bold">elsif</b> <i class="emphasis">boolean_</i>expression <b class="bold">then</b>          { sequential_statement } }     [ <b class="bold">else</b>          { sequential_statement } ]     end if [ <i class="emphasis">if</i>_label ] ;

At first sight, this may appear somewhat complicated,...