The models that we have used as examples in preceding chapters all have fixed behavior and structure. In many respects, this is a limitation, and we would like to be able to write more general, or generic, models. VHDL-AMS provides us with a mechanism, called generics, for writing parameterized models. We discuss generics in this chapter and show how they may be used to write families of models with varying behavior and structure.

12.1 Parameterizing Behavior

We can write a generic entity by including a generic interface list in its declaration that defines the formal generic constants that parameterize the entity. The extended syntax rule for entity declarations including generics is

entity_declaration <span class="unicode">?</span>     <b class="bold">entity</b> identifier <b class="bold">is</b>          [ <b class="bold">generic</b> ( <i class="emphasis">generic</i>_interface_list) ; ]          [ <b class="bold">port</b> (<i class="emphasis">port</i>_interface_list) ; ]          {entity_declarative_item }      [ <b class="bold">begin</b>          { concurrent_assertion_statement               <i class="emphasis">passive</i>_concurrent_procedure_call_statement               <i class="emphasis">passive</i>_process_statement } ]      <b class="bold">end</b> [ <b class="bold">entity</b> ] [ identifier ] ;

The difference between this and the simpler rule we have seen before is...