When we write complex behavioral models it is useful to divide the code into sections, each dealing with a relatively self-contained part of the behavior. VHDL-AMS provides a subprogram facility to let us do this. In this chapter, we look at the two kinds of subprograms: procedures and functions. The difference between the two is that a procedure encapsulates a collection of sequential statements that are executed for their effect, whereas a function encapsulates a collection of statements that compute a result. Thus a procedure is a generalization of a statement, whereas a function is a generalization of an expression. Also in this chapter we examine simultaneous procedural statements, which are related to functions but are used to express analog behavior.

9.1 Procedures

We start our discussion of subprograms with procedures. There are two aspects to using procedures in a model: first the procedure is declared, then elsewhere the procedure is called. The syntax rule for a procedure declaration is

subprogram_body <span class="unicode">?</span>   <b class="bold">procedure</b> identifier [( <i class="emphasis">parameter</i>_interface_list )]<b class="bold">is</b>       { subprogram_declarative_part }   <b class="bold">begin</b>       { sequential_statement }   <b class="bold">end</b> [ <b class="bold">procedure</b> ][ identifier ];

For now we will just look at procedures without the parameter list part; we will come back to parameters in the next section.

The identifier in a procedure declaration names the procedure. The name may be repeated at the end of the procedure...