TABLE OF CONTENTS A VHDL-AMS description of a design is usually used to simulate the design and perhaps to synthesize the hardware. This involves processing the description using computer-based tools to create a simulation program to run or a hardware net-list to build. Both simulation and synthesis require two preparatory steps: analysis and elaboration. Simulation then involves executing the elaborated model, whereas synthesis involves creating a net-list of primitive circuit elements that perform the same function as the elaborated model. In this section, we look at the analysis, elaboration and execution operations introduced in Chapter 1.
The first step in processing a design is to analyze the VHDL-AMS descriptions. A correct description must conform to the rules of syntax and semantics that we have discussed at length. An analyzer is a tool that verifies this. If a description fails to meet a rule, the analyzer provides a message indicating the location of the problem and which rule was broken. We can then correct the error and retry the analysis. Another task performed by the analyzer in most VHDL-AMS systems is to translate the description into an internal form more easily processed by the remaining tools. Whether such a translation is done or not, the analyzer places each successfully analyzed description into a design library.
A complete VHDL-AMS description usually consists of a number of entity declarations and their corresponding architecture bodies. Each of these is called a design unit. Organizing a design as a hierarchy of modules, rather than...
