TABLE OF CONTENTS In Chapter 1 we introduced terminals as the VHDL-AMS feature for representing the physical connection points or circuit nodes of a system. Recall that terminals are declared to be of various natures, which represent different energy domains of a system. We also introduced branch quantities as the VHDL-AMS feature for accessing the effort and flow aspects of terminal. In this chapter, we explore these concepts in detail.
Let us start with the syntax rule for a terminal declaration and then show some examples. The syntax rule is
terminal_declaration <span class="unicode">?</span> <b class="bold">terminal</b> identifier { , <span class="unicode"> </span> }: subnature_indication ;A terminal declaration can appear as a declarative item before the keyword begin in an architecture body. The declaration names one or more terminal objects of a particular nature. The nature of a terminal determines the across and through types for the terminal, which represent the effort and flow aspects of the energy domain for the terminal.
To illustrate declaration of terminals, consider the following example:
<b class="bold">subtype</b> voltage <b class="bold">is</b> real <b class="bold">tolerance</b> "low_voltage";<b class="bold">subtype</b> current <b class="bold">is</b> real <b class="bold">tolerance</b> "low_current";<b class="bold">nature</b> electrical <b class="bold">is</b> voltage <b class="bold">across</b> current <b class="bold">through</b> electrical_ref <b class="bold">reference;</b><b class="bold">terminal</b> anode, cathode : electrical;
The subtype and nature declarations model the electrical energy domain, as we have seen. The terminal declaration then names two terminals, anode and cathode, each of which is of the electrical nature. The across type associated with...
