Packages in VHDL-AMS provide an important way of organizing the data and subprograms declared in a model. In this chapter, we describe the basics of packages and show how they may be used. We also look at several predefined and standard packages, which provide types, natures and operators for use in VHDL-AMS models.

10.1 Package Declarations

A VHDL-AMS package is simply a way of grouping a collection of related declarations that serve a common purpose. They might be a set of subprograms that provide operations on a particular type of data, or they might just be the set of declarations needed to model a particular design. The important thing is that they can be collected together into a separate design unit that can be worked on independently and reused in different parts of a model.

Another important aspect of packages is that they separate the external view of the items they declare from the implementation of those items. The external view is specified in a package declaration, whereas the implementation is defined in a separate package body. We will look at package declaration first and return to the package body shortly.

The syntax rule for writing a package declaration is

package_declaration <span class="unicode">?</span>   <b class="bold">package</b> identifier <b class="bold">is</b>      { package_declarative_item }   <b class="bold">end </b>[ <b class="bold">package</b> ] [ identifier ] ;

The identifier provides a name for the package, which we can use elsewhere in a model to refer...